Growing research and development efforts are being made for high-density semiconductor integrated circuit devices with an emphasis put on a very large-scale integration provided with an increased number of component function blocks which have been fabricated on separate semiconductor chips. A typical example of the very large-scale integration is shown in FIG. 1 and comprises a plurality of component function blocks 1, 2, 3 and 4 fabricated on a single semiconductor chip 5 and electrically connected to a group of signal input pins 6, a group of signal output pins 7 and one another. After fabrication of the very large-scale integration, the component function blocks are tested whether or not each component function block performs an operation expected thereto. For this reason, the very large-scale integration of the type having the component function blocks is provided with a test control circuit and a typical example of the test control circuit is shown in FIG. 2 of the drawings.
Referring to FIG. 2 of the drawings, the prior-art test control circuit is shown together with component function blocks 8, 9 and 10 capable of achieving respective predetermined functions identical with one another. The prior-art test control circuit comprises plural groups of selector circuits associated with the respective component function blocks 8, 9 and 10, but only one selector circuit of each group is illustrated and designated by 11, 12 or 13. The selector circuit 11 has two input nodes one of which is supplied with one data bit of a first external data signal (two data bits of which are labeled I.sub.01 and I.sub.11) and the other of which is supplied with one data bit of an external test signal (two bits of which are labeled I.sub.21 and I.sub.22). The selector circuit 12 also has two input nodes one of which is supplied with one data bit a second external data signal (two bits of which are labeled I.sub.02 and I.sub.12) and other of which is supplied with the data bit I.sub.21 of the external test signal. Similarly, the selector circuit 13 has two input nodes one of which is supplied with one data bit of a third external data signal (two bits of which are labeled I.sub.03 and I.sub.13 ) and the other of which is supplied with the data bit I.sub.21 of the external test signal. All of the selector circuits associated with the component function block 8 are responsive to a control signal S1 and transfer either first external data signal or the external test signal to the component function block 8. In the similar manner, the selector circuits associated with the component function blocks 9 and 10 are responsive to the control signal S1 and transfer either second and third external data signals or the external test signal to the component function blocks 9 and 10, respectively. When the component function blocks 8, 9 and 10 are supplied with the first, second and third external data signals, respectively, the component function blocks 8, 9 and 10 carry out the predetermined operations and produce first, second and third output signals S2, S3 and S4 each consisting of a plurality of data bits. The first, second and third output signals S2, S3 and S4 are fed to a selector circuit 14 which is responsive to a control signal S5 and operative to transfer one of the first, second and third output signals S2, S3 and S4 to a group of output terminals 15.
In order to examine the component function blocks, the control signal S1 causes all of the selector circuits to transfer the external test signal to the component function blocks 8, 9 and 10. Then, the component function blocks 8, 9 and 10 achieve the predetermined functions and produce the first, second and third output signals S2, S3 and S4 based on the common external test signal. All of the output signals S2, S3 and S4 are supplied to the selector circuit 14 so that the selector circuit 14 successively transfers the first, second and third output signals S2, S3 and S4 to the output terminals 15 with changing the control signal S5. Then, the component function blocks 8, 9 and 10 are examined by comparing the first, second and third output signals S2, S3 and S4 with an expected value. However, a problem is encountered in the prior-art test control circuit in that a long period of time is needed to achieve the test operation for all of the component function blocks. This is because of the fact that the all of the output signals from the component function blocks are successively read out through the selector circuit 14 even if some of the component function blocks are designed to achieve the predetermined functions identical to one another.
One approach to solve the problem encountered in the prior art test control circuit shown in FIG. 2 is illustrated in FIG. 3 of the drawings together with the component function blocks 21 and 22 achieving respective predetermined functions identical with each other. The test circuit illustrated in FIG. 3 comprises two groups of selector circuits 23 to 28 operative to transfer either first and second external data signals or a common external test signal S6 to the respective component function blocks 21 and 22 depending upon a control signal S7. When either first and second external data signals or the common external test signal S6 are supplied to the component function blocks 21 and 22, the component function blocks 21 and 22 perform the predetermined operations and produce first and second output signals S8 and S9, respectively which are supplied to a group of AND gates 29. Then, the first output signal S8 is ANDed with the second output signal S9 to produce an output signal S10. The component function blocks 21 and 22 are supplied with the common external test signal S6 so that the first output signal S8 is identical in bit string with the second output signal S9 and further to the output signal S10 of the AND gates 29 in so far as the component function blocks 21 and 22 have no trouble. As a result, the component function blocks 21 and 22 are concurrently examined based on the output signal S10. The test control circuit illustrated in FIG. 3 can examine the component function blocks 21 and 22 with the identical functions in a short period of time in comparison with the prior-art test control circuit illustrated in FIG. 2. However, another problem is encountered in the test control circuit illustrated in FIG. 3 in reliability. Namely, if the AND gates 29 have a trouble and produce an output signal S10 identical in bit string to the expected result in spite of difference in bit string between the first and second output signals S8 and S9, the component function blocks would be evaluated to be excellent in quality.